The present invention relates to a semiconductor integrated circuit device and a method of testing the same, or in particular to a large-scale integrated circuit device operated by a high-frequency clock signal and a technique effectively utilized for a method of testing the device.
U.S. Pat. No. 5,173,906 issued on Dec. 22, 1992, JP-B-2614413 (corresponding to JP-A-7-93998) issued May 28, 1997 and U.S. Pat. No. 5,557,619 issued on Sep. 17, 1996 each disclose a method of testing the RAM (random access memory) mounted on a large-scale integrated circuit (LSI) using a built-in self test (hereinafter referred to as xe2x80x9cBISTxe2x80x9d) circuit. The test methods proposed in these patents use a BIST circuit including a flip-flop circuit FF with a scan circuit. According to this these test methods, (1) the BIST circuit for the RAM (hereinafter referred to as xe2x80x9cRAM-BIST circuitxe2x80x9d) is set using a scan circuit, (2) the RAM is tested by applying a clock of a frequency beyond the processing capacity of an evaluation tester to the LSI using the RAM-BIST, and (3) the test result is recovered using the scan circuit (in low frequency cycles).
In the prior art, as described above, the RAM is tested in cycles of a clock frequency beyond the processing capacity of the evaluation tester in such a manner that a clock is first applied with a frequency that can be processed by the evaluation tester, the registers of the RAM-BIST circuit are set and then the clock cycles are increased to a high frequency at which the RAM is to be tested. As an alternative, after the clock is stopped, the clock of the desired frequency is applied anew and the RAM test is conducted. Also, in order to recover the result of the RAM test, the frequency of the clock cycles at which the RAM is tested is decreased to the cycles of the frequency which can be processed by the evaluation tester. As still another alternative, after the clock is stopped, the clock of frequency cycles which can be processed by the evaluation tester is applied anew and the value of the registers storing the RAM test result is recovered.
With the increase in the density and the operating speed of each element in the LSI, the noises of the power supply for LSI operation are on the increase. The present inventors have discovered that a large power noise is generated by the abrupt impedance change of the LSI with respect to the power supply at the time of starting or stopping the clock application. This power noise may unduly rewrite the data of the registers in the LSI. In the case where a register write error is caused by the power noise, therefore, the information set in the RAM-BIST circuit for the RAM is destroyed and the normal test operation becomes impossible. The information on the test result is also destroyed and the correct test result cannot be obtained. In other words, the well-known cases described above fail to take any protective measure against the operation error due to the power noise generated by the supply or stop of the clock signal or the change in clock frequency.
The study by the inventors shows that the power noise is generated at the time of stopping/starting the clock probably by the following facts. As described above, with the increase in density of the LSI and the resulting sharp increase in the number of the flip-flop circuits FFs mounted on the LSI (i.e. the number of the elements connected to the clock signal), an increased amount of current is consumed at the time of starting to supply the clock signal due to the high density of the LSI. The power noise (the fluctuation of the source voltage or the grounding potential) is proportional to the product of the change in current consumption and the impedance of the power supply system. Specifically, the greater the change in power consumption or the higher the impedance of the power system, the larger the power noise. When testing the LSI completed on a semiconductor wafer, power is supplied by xe2x80x9capplying a probexe2x80x9d or the like method, and therefore the impedance of the power system is often higher than when the LSI is used with an actual product. Thus, the power noise poses a more serious problem.
The present inventors have encountered the problem of the power noise while developing a most sophisticated product. The experiments conducted by the inventors show that a power noise of about 10 MHz having an amplitude of 0.7 V is generated for a source voltage of 1.5 V the instant the clock signal begins to be supplied. In the environment where this power noise is generated, the data stored in the internal registers of the LSI is destroyed and it becomes difficult to conduct a correct LSI test. This indicates that the power noise cannot be reduced by the conventional approach in which the frequency is switched slowly to a lower value that can be processed by the evaluation tester. In order to radically reduce the power noise by reducing the impedance of the power system, it is common practice to embed a high-pass capacitor for reducing the power noise in the LSI. This would result in occupation of a great area on the chip and fails to provide a satisfactory solution.
The present inventors have taken note of the fact that the frequency of the power noise of the LSI having an increased density and an improved performance is low relative to the operation cycles of the LSI. In other words, the inventors have found that the noise generated the instant the clock signal begins to be supplied has a frequency of about 10 MHz as described above, and in the case where a clock signal of about 500 MHz to 800 MHz sufficiently higher than 10 MHz is supplied to the LSI, the noise generated in the power line is as small as several tens of mV. This reduction in noise amplitude is probably due to the fact that the power noise xe2x80x9ccannot followxe2x80x9d the operating frequency of the clock signal which is higher than the resonance frequency (about 10 MHz) in a resonance circuit having a parasitic capacitance, a parasitic inductance component and a wiring resistance at the power terminal. Actually, it has been confirmed by experiments that the power noise measured with the LSI operating frequency of 800 MHz is as small as about several tens of mV. Taking advantage of this fact, the present inventors have come to develop a method of testing a high-density, high-performance semiconductor integrated circuit device.
An object of the present invention is to provide a semiconductor integrated circuit device having a high density, a high performance and a high reliability and a method of testing it.
Another object of the invention is to provide a semiconductor integrated circuit device having a high density, a high performance and a high reliability and a method of testing the device with a shorter testing time.
The above and other objects and novel features of the invention will be made apparent by the detailed description taken in conjunction with the accompanying drawings.
According to one aspect of the invention, there is provided a semiconductor integrated circuit device comprising a test circuit including a first latch circuit for holding a test pattern inputted to an electronic circuit operating in accordance with the clock signal and a second latch circuit for holding an output circuit of the electronic circuit corresponding to the test pattern, wherein the electronic circuit and the test circuit are supplied continuously with a clock signal having a higher frequency than the noise frequency generated in the power line at the time of starting to supply the clock signal to the electronic circuit, while at the same time performing the operation of inputting the test pattern to the first latch circuit and the operation of outputting the output signal held in the second latch circuit, in accordance with the clock signal with a period longer than the period of the clock signal.
According to another aspect of the invention, there is provided a method of testing a semiconductor integrated circuit device comprising a test circuit including a first latch circuit for holding a test pattern inputted to an electronic circuit operating in accordance with the clock signal and a second latch circuit for holding an output circuit of the electronic circuit corresponding to the test pattern, wherein the electronic circuit and the test circuit are supplied continuously with a clock signal having a higher frequency than the noise frequency generated in the power line at the time of starting to supply the clock signal to the electronic circuit, while at the same time performing the operation of inputting the test pattern to the first latch circuit and the operation of outputting the output signal held in the second latch circuit, in accordance with the clock signal with a period longer than the period of the clock signal.